This invention relates to programmable logic device integrated circuits and generally similar circuitry, all of which are generically referred to herein as programmable logic devices or PLDs. More particularly, the invention relates to high-speed serial data transceiver circuitry for use on PLDS.
PLDs are relatively general-purpose devices that are designed to be able to satisfy a wide range of needs. There is increasing interest in the use of high-speed serial data communication for exchange of information between the devices that make up various kinds of systems. There are many possible “protocols” for such high-speed serial communication. Some of these protocols may be industry-standard protocols. Other protocols may be custom-designed for particular systems. A particular protocol typically involves such things as how is the data formatted; how many channels are used together to provide the overall communication link; at what speed (serial data rate or bit rate) is a channel operated; if multiple channels are employed to provide a link, how much skew (differential delay) can there be between the channels; etc. With regard to speed, there is always a desire for faster communication. For example, speeds up to about 6 Gbps (gigabits per second) are now being routinely employed, and speeds up to 10-12 Gbps are anticipated or are starting to be used.
It is a considerable challenge to design a PLD that can support a wide range of possible serial data communication speeds, including speeds at the upper end of the ranges mentioned above.